The Intel Larrabee is still in concept design stages as of press time, but data gathered from a recent press conference from the Larrabee project's top engineer, Dr. Larry Seller, has lead many to believe that the CPU will have a graphics processing unit integrated on die - or at least an architecture for graphics processing.

According to the tech wizards at AnandTech, the Larrabee will still be based on the Pentium architecture (x86), although it will be a multi-core (many have called it "many core") processor of an unknown number of cores and be realized as a data parallel processing powerhouse (think Cell BE).

Now the general notion of what the Larrabee is supposed to do is often confused, thanks to the rumors of this mythical CPU-with-GPU that ran amok. Now that the principle facts are known, it appears that Larabee was not designed essentially to be a replacement for dedicated graphics computing. Don't get us wrong: the Larabee can perform graphics rendering on its own, but it's not expected to defeat discrete graphics solutions by much.

In fact, the first few details of what the Larrabee will do involves a tie-in of deferred tile-based rendering (ala Imagination Technologies' PowerVR graphics chip) and a back-end frame buffer rendering process and neither promises much in the way of quality.

The multi-core CPU, however, will have a fully coherent memory subsystem for its multi-chip setup, and from here you get a clearer idea that it's geared more for performance.

So it's more of a CPU that can process DirectX and OpenGL instructions, if told to. And by using a combination of an extension of the x86 instruction set and an Intel-developed programming language in C/C++ designed specifically for the Larrabee, the CPU can even perform as a custom processing solution for software designed to run it as an engine of sorts.

A bigger picture of that would be slapping it into a game console, allowing developers to use the specialized SDK and create their own engine. Of course, to be this diverse, the processor will have to be very open. Thus, Larrabee, doesn't have many fixed function logic. The more complex instructions will have to come from software, no doubt.

The Larrabee was claimed to be heavily modified to carry a 16-ALU-wide vector unit with it, while each core would have a coherent memory foundation including Level 1 caches (unknown capacity) and a secondary level cache of some 256 KB.

The processor would have 1024-bit ring bus interconnecting all the cores in the processor, serving as the data and instruction pathways for all cores. The ring bus is two way, with 512-bits coming to and from each neighboring core.

We'll have more updates on the Larrabee as soon as more is spilled. But if you want to get yourself in the tech mood now, AnandTech has a lengthy writeup for your perusal.

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